Inverter control system

ABSTRACT

An inverter in the D.C. power transmission is controlled by gate pulses which are synchronized with voltages of an A.C. system and whose interval is constant for respective arms of the inverter. Simultaneously therewith, in order to prevent the inverter from causing a commutation failure due to a fault in the A.C. system, a control voltage for making the gate pulses is corrected by the use of the lowest one of the phase voltages or line voltages of the A.C. system. The control voltage becomes greater as the phase voltage or the line voltage lowers more from a rated voltage. When the control voltage increases, the gate pulses are provided at a timing of a larger advanced control angle so as to maintain the extinction angle constant.

BACKGROUND OF THE INVENTION

This invention relates to an inverter control system in the D.C. powertransmission, and more particularly to a control system which issuitable in case of controlling the gate pulse interval to be constant.

As a phase control system for the gate pulses of an inverter in the D.C.power transmission, the so-called each-phase control system has hithertobeen adopted. It determines the phases of the gate pulses of therespective arms of the inverter in such way that gate pulse phaseshifters which employ the commutation voltages of the respective armsfor their synchronizing power sources are disposed in correspondencewith thyristor valves of the arms. In order to perform a stableoperation without any commutation failure even when a balance orunbalance fault occurs in an A.C. system on the inverter side in thecase of adopting such each-phase control system, control may be made,for example, so as to attain a prescribed extinction angle γ_(o) bydetecting a drop of the commutation voltage and increasing the advancedcontrol angle β to the amount of an increment of the overlapping angleascribable to the drop of the commutation voltage as has been proposedin patent application Ser. No. 78,575/1969.

The control of increasing the advanced control angle β in dependence onthe drop of the commutation voltage, however, cannot always achieve thestable operation in case of using a gate pulse phase shifter, asproposed in patent application Ser. No. 129,412/1972, by which phaseshifts of the synchronizing power sources are averaged by means of avoltage-controlled oscillator so as to render the gate pulse intervalconstant. This is obvious when, by way of example, a drop of the phasevoltage is supposed. Even if the phase of one commutation voltage leads,that of another commutation voltage will lag to the same amount, so thatthe averaged phase variation is zero. The foregoing control ofincreasing the advanced control angle β according to the drop of thecommutation voltage cannot cope with the changes of the phases of thecommutation voltages. Therefore, the arm at which the phase of thecommutation voltage leads falls into an insufficient extinction angleand can cause a commutation failure.

SUMMARY OF THE INVENTION

It is accordingly an object of this invention to provide an invertercontrol system which is so contrived that, when a fault takes place inan A.C. system, the phase of a gate pulse can be instantly controlled inthe direction of stabilizing the operation of an inverter.

This invention intends to accomplish the object by separately disposingmeans to output the gate pulses accurately at a fixed interval and meansto shift the phases of the gate pulses, to be bestowed on the inverter,in dependence on the state of operation and by introducing into thephase shifting means a signal corresponding to the state of voltages inthe A.C. system.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a connection diagram showing the arrangement of an inverter inthe D.C. power transmission,

FIG. 2 is a waveform diagram for explaining phase changes of linevoltages at a fault of an A.C. system,

FIGS. 3 and 4 are vector diagrams for explaining voltages at theone-line earthing fault and two-line earthing fault of the A.C. system,respectively,

FIGS. 5 to 7 are graphs for explaining advanced control angles requiredfor the inverter at the faults of the A.C. system,

FIG. 8 is a vector diagram for explaining voltages at the two-lineshort-circuit of the A.C. system,

FIGS. 9 and 10 are graphs for explaining voltage drops and phase shiftsat the two-line short-circuit fault of the A.C. system,

FIG. 11 is a block diagram showing the essential portions of anembodiment of this invention,

FIG. 12 is a diagram showing an example of the characteristic of acircuit to be used in the embodiment in FIG. 11,

FIGS. 13 and 14 are block diagrams for explaining examples of concretecircuits for generating gate pulses at a fixed interval as can beemployed in this invention, respectively, and

FIG. 15 is a waveform diagram for explaining the operation of thecircuit in FIG. 14.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

As previously stated, this invention realizes the control of fixing thegate pulse interval, and further, prevents an inverter from failing incommutation even at faults occurring in an A.C. system. Hereunder thisinvention will be explained in detail in conjunction with an embodiment.First of all, description will be made of what influences the faults ofthe A.C. system have on the inverter.

An example of a D.C. power transmission system is shown in FIG. 1.Referring to the figure, T designates a transformer, V₁ -V₆ arms of aninverter as constructed of thyristor valves, and L_(DC) a D.C. reactor.A D.C. side input of the inverter is connected through D.C. lines toremote terminals. A.C. side terminals of the transformer T are connectedto an A.C. system, the respective phases of which have voltages V_(a),V_(b) and V_(c). The voltages are detected through voltage or potentialtransformers PT_(a), PT_(b) and PT_(c) and are delivered to a controlcircuit (not shown) including a gate pulse phase shifter, respectively.DCCT denotes a D.C. current transformer, while VI indicates a current -voltage converter. The remote terminals are of the same arrangement.

Normally, the three-phase voltages V_(a), V_(b) and V_(c) are balancedas shown by solid-line waveforms in FIG. 2. Now, let's consider a casewhere the one-line earthing occurs in the A.C. system and where thevoltage V_(a) of the phase-a drops as shown at V_(a) ' by a broken line.Where the transformer connection is the star-star connection ( ) as inFIG. 1, the commutation voltages are equal to the line voltages, andtheir zero points are intersection points of the phase voltages.Accordingly, when the voltage V_(a) lowers to V_(a) ', the phase of theintersection point or that of the commutation voltage leads by φ at thephase-b and lags by φ at the phase-c as illustrated in FIG. 2. While thecommutation voltage also drops, the rate is smaller than the drop rateof the phase voltage. This state is illustrated in FIG. 3 by a vectordiagram. The magnitude of the phase voltage is now let to be p in thep.u. value (normalized value) whose base is the rated phase voltageV.sub. a (OA in FIG. 3). The line voltage (commutation voltage) in thecase where the phase voltage is p, is assumed to become q in the p.u.value whose base is the rated line voltage (CA or AB). Let φ indicatethe change of the phase of the line voltage in the case where the phasevoltage drops from 1 to p in the p.u. value. Then, the relationshipamong p, q and φ is easily obtained by drawing a diagram and becomes asin FIG. 5. In case of the earthing of two lines, for example, theearthing of the phase-a and phase-b, a vector diagram is as in FIG. 4.In this case, the line voltage between the phase-a and phase-b drops ata rate equal to that of the phase voltage, and it becomes p likewise tothe phase voltage in terms of the p.u. value having the foregoing base.The magnitude of the line voltages between the phase-c and phase-a andbetween the phase-b and phase-c becomes q as in the case of the one-lineearthing. The magnitude of the changes of the phases similarly becomes φas shown in the figure.

In case of the three-line earthing, the line voltage is p at all thethree phases, and no phase change is involved.

As is well known, the relation among the commutation voltage, theextinction angle γ and the advanced control angle β is expressed by:##EQU1## where γ denotes the extinction angle, β the advanced controlangle, E_(a) the commutation voltage, I_(d) the D.C. current, and x thecommutation reactance (in Ω). The reference of the phases of the anglesγ and β is the zero point of the commutation voltage.

Let X indicate the commutation reactance in the p.u. value whose base isthe capacity of the transformer, and z indicate the D.C. current in thep.u. value whose base is the rated value thereof. Then, Eq. (1) becomesas follows:

    cos γ - cos β = X. (z/q)                        (2)

Now, consider a case where X= 0.2 and z= 0.1. How the advanced controlangle β need be controlled with changes of q in order to keep theextinction angle γ at 20degrees in this case, has been calculated and isillustrated at A in FIG. 6.

In the each-phase control, the gate pulses are generated in synchronismwith the phases of the cummutation voltages after the change of thephase voltage as previously stated by citing patent application Ser. No.78,575/1969, and hence, control voltages corresponding to the curve A inFIG. 6 may be bestowed on the gate pulse phase shifter.

With the pulse phase shifter of the gate pulse interval-fixing system asproposed in the cited patent application Ser. No. 129,412/1972, however,the inverter cannot be stably operated by the above method in some casesas previously stated. The reason will now be explained by taking as anexample the case of the one-line earthing (to which the vector diagramof FIG. 3 corresponds). The gate pulse phase shifter disclosed in thepatent application operates by making use of the zero points of thecommutation voltages as synchronizing pulses. When the voltage V_(a)lowers to the value V_(a) ', the positions of the synchronizing pulseschange by φ or - φ as indicated by pulses at SP in FIG. 2. Since,however, the gate pulse phase shifter determines the gate phase withreference to the mean value, φ and - φ cancel each other, andultimately, the phasic position before the change or the zero point ofthe line voltage at the voltage balance becomes the reference.

By way of example, consider the commutation from the arm V₅ to the armV₁ in FIG. 1. The advanced control angle β shown by the curve A in FIG.6 corresponds to a period from a commutation initiating time S to thezero point O' of the line voltage as indicated in FIG. 2. Herein, theextinction angle γ is obtained as indicated in FIG. 2. In the case ofthe conventional each-phase control, the gate phase is determined withreference to the point O', and hence, the control voltage conforming tothe curve A in FIG. 6 may be given to the gate pulse phase shifter. Onthe other hand, in the case of the control of rendering the gate pulseinterval constant, the gate phase is determined with reference to apoint O even at the one-line earthing. The control voltage needtherefore be given to the gate pulse phase shifter so that the advancedcontrol angle may become β + φ = β_(AP).

The value of β_(AP) is illustrated at a curve B in FIG. 6. At, forexample, q== 0.9, FIG. 5 teaches p= 0.8 and φ= 3 (degrees), andtherefore, the curve B has been obtained by adding 3 degrees to thecurve A.

In the case of the three-line earthing, the phases of the commutationvoltages do not change, and the control may be made so as to attain thecurve A.

In the case of the two-line earthing, as understood from FIG. 4, thereare the phases which ought to be controlled as the curve B and the phasewhich may be controlled as the curve A. Even when only one phase failsin commutation, the running of the inverter is impossible. After all,the control need be made so as to attain the curve B.

In this manner, in the case of performing the gate pulse interval-fixingcontrol, the system which merely corrects the control signal incorrespondence with the drop of the commutation voltage so as toincrease the advanced control angle β is not preferable because thecontrol method differs greatly in dependence on the kind of the faults.That is, it necessitates a complicated and expensive circuit and is lessreliable that when any fault of the A.C. system takes place, the sort ofthe fault is discriminated to change-over the control methods.

This invention does not take notice of the mere commutation voltage, butit utilizes the phase voltages and the line voltages on the A.C. side ofthe transformer for the inverter. It proposes that, in case where anyfault occurs in the A.C. system and where a voltage drop arises, thelowest one of the phase voltages or the line voltages is selected,whereupon the control signal of the gate pulse phase shifter iscorrected so as to determine the advanced control angle β in dependenceon the drop width of the particular voltage.

It will be explained that controls dependent upon the phase voltages maybe made when the earthing faults take place.

FIG. 7 illustrates what values the advanced control angle β should bemade according to the drop of the phase voltage p. In the figure, acurve C indicates the case of the three-phase short-circuit. In thiscase, the values p (phase voltages) and q (line voltages) lower at theequal rates, and no phase difference is involved. Therefore, the curve Cis the same as the curve A in FIG. 6. As regards a curve D in FIG. 7,the values q corresponding to the values p are evaluated from FIG. 5,and the values β are obtained by substituting the evaluated values intoEq. (2). The reference of the values is the zero point of thecommutation voltage at the fault (the point O' in FIG. 2). As in thecalculation stated before, X= 0.2 and I_(d) = 1.0.

In the control of rendering the gate pulse interval constant, it isnecessary to determine the advanced control angle β with reference tothe point O in FIG. 2. The values β are obtained by adding the phasechange φ in FIG. 2 to the curve D, and become as indicated by a curve E.

In the case of the two-line earthing, as in the previous explanation,there are the phase to be controlled as the curve C and the phases to becontrolled as the curve E. In order to stably effect all thecommutations, a larger value between the values C and E need beselected. On the other side, it is usual in the D.C. power transmissionsystem that the running is stopped when p becomes smaller than 0.5 inthe case of the two-line or three-line earthing. As apparent from FIG.7, the curves C and E are very close in a range of p≧ 0.5. Inconclusion, by making the control as the curve E in the whole range ofp, the inverter having the gate pulse interval controlled to be constantcan be stably operated even when the earthing faults take place.

Description will now be made of a case of the two-line short-circuitfault.

A vector diagram in this case is shown in FIG. 8. In the figure, pdenotes the magnitude of the phase voltage at the fault by letting avalue of the phase voltage in the normalcy (OA in the figure) be 1 p.u.,while q and q' denote the magnitudes of the line voltages at the faultby letting a value of the line voltage in the normalcy (AB etc. in thefigure) be 1 p.u.

Assuming that the transformer for the inverter is of the star - starconnection ( ), the commutation voltages are equal to the line voltages.

FIG. 9 illustrates the relations between the quantity p and thequantities q, q' and φ (the change of the phases of the line voltages).When the relation between the values p and q' is referred to, thequantity q' exhibits a larger drop width. In the case of the two-lineshort-circuit, accordingly, it is not satisfactory to increase theadvanced control angle β in dependence on the drops of the phasevoltages as in the cases of the earthing faults, and it is better tomake the control in dependence on the drops of the line voltages. FIG.10 illustrates the relation between the line voltage q' between thephases a and b and the commutation voltage and the relation between theline voltage q' and the phase change of the commutation voltage. Symbolsq, q' and φ are equivalent to those in FIG. 8.

There has been calculated what values the advanced control angle β maybe made where the line voltages lower to the values q and q' as in FIG.8 due to the two-line short-circuit. The result is included as a curve Gin FIG. 7. Here, regarding the curve G, the axis of abscissas representsthe line voltage q' between the phases a and b. It has been evaluated inthe same way as in the cases of the earthing faults. More specifically,in the case of the two-line short-circuit of the phases a and b as inFIG. 8, the voltage of the commutation from the arm V₁ to the arm V₃ inFIG. 1 is equal to q', and the phase does not change. Therefore, theadvanced control angle for keeping the extinction angle of 20° becomesthe curve C in FIG. 7. The voltage of the commutation from the arm V₃ tothe arm V₅ is equal in magnitude to q, and leads in phase by φ over thenormal condition. Therefore, the value β for the magnitude qcorresponding to the value q' in FIG. 10 is evaluated by Eq. (2), thevalue φ corresponding to the same value q' is obtained from FIG. 10 andis added to the evaluated value β, and a control voltage correspondingto the resultant value (β + φ) may be impressed on the gate pulse phaseshifter. Obtained in this way is the curve G in FIG. 7. In the case ofthe two-line short-circuit, the extinction angle of 20 degrees can beheld by performing the control along the curve G.

As understood from FIG. 7, the curve E obtained as to the earthing faultby taking the phase voltage p on the axis of abscissas and the curve Gobtained as to the short-circuit fault by taking the line voltage q' onthe axis of abscissas are in close proximity.

Accordingly, an inverter control system which can cope with any of theearthing and short-circuit faults can be acquired by the method ofselecting the lowest one of the line voltages or the phase voltages andincreasing the advanced control angle β in correspondence with thelowering width of the selected voltage.

FIG. 11 shows an example of a circuit which concretely actualizes suchidea of this invention. The embodiment intends to exceute the controlthrough the approximation of the curve E by a straight line F in FIG. 7.In FIG. 11, AP indicates the gate pulse phase shifter of the gate pulseinterval-fixing control system. V_(a), V_(b) and V_(c) representsynchronizing power sources, which are respectively led from thepotential transformers PT_(a), PT_(b) and PT_(c). Output firing pulsesP₁ -P₆ become the gate pulses of the arms constructed of the thyristorvalves V₁ -V₆ in FIG. 1. The gate pulse phase shifter shall have acharacteristic in which, as illustrated in FIG. 12, the control inputvoltage E_(c) and the retarded control angle of the output α areproportional. Concrete examples will be explained later with referenceto FIGS. 13 and 14.

Full-wave rectifier bridges B₁ -B₆ rectify the phase voltages V_(a),V_(b) and V_(c) and line voltages V_(ab), V_(bc) and V_(ca) of the A.C.system and convert them into D.C. voltages, respectively. Resistors R₁and R₂ and a capacitor C₁ constitute a circuit which divide and smooththe output voltage of each of the bridges B₁ -B₆.

Diodes D₁ -D₆ and a resistor R₃, which has a resistance higher than thatof the resistor R₂, are connected to a positive power source + E_(s). Avoltage of the smallest absolute value among the voltages across thecapacitors C₁ is selected by this circuit. Voltages to be applied to thediodes D₁ -D₆ are any positive voltages. The diode of the least positivevoltage, namely, of the lowest potential turns "on," whereas the otherdiodes are reverse-biased. It is therefore apparent that the aboveselection is made. A buffer amplifier AB has a high input impedance anda low output impedance, and the polarities of its output and inputvoltages shall be the same. A₁ and A₂ designate operational amplifiers,and R₄ denotes a resistor. A bias voltage V_(BB) is equal in theabsolute value to the output of the amplifier AB in the case where thephase voltage has the rated value (p= 1), and it is opposite in thepolarity thereto (that is, it is a negative voltage). Since theamplifier A₁ adds the output voltage of the amplifier AB and the biasvoltage V_(BB) and inverts the polarity of the sum, the output of theamplifier A₁ is zero at p= 1. As the value p becomes smaller, thepositive voltage becomes larger linearly. A diode D₇ serves to preventthe output of the amplifier A₁ from becoming positive. Accordingly, whenthe phase voltage of the A.C. system exceeds the rated voltage (at p>1), the output of the amplifier A₁ becomes zero. Similarly, theoperational amplifier A₂ adds three inputs and inverts the polarity ofthe sum. The first of the three inputs is the output of the operationalamplifier A₁, the second is a voltage into which the output current ofthe current transformer DCCT in FIG. 1 has been converted (that is, theoutput of the current - voltage converter VI), and the third is a biasvoltage V_(BB) '.

Although this invention does not specifically intend a control for avariation of a current of the D.C. transmission lines, it is necessaryin case of intending to hold the extinction angle constant that, withthe increase of the D.C. current, the advanced control angle β islinearly increased (the retarded control angle α is linearly decreased).The amplifier A₂ is a circuit therefor. Consider the case where the A.C.voltages are of the rated values. In this case, the output of theamplifier A₁ is zero. Accordingly, the control voltage E_(c) of the gatepulse phase shifter (the output voltage of the amplifier A₂) changes independence on only the value of the D.C. current I_(d). It is naturalthat the bias voltage V_(BB) ' is made a value at which, when thecurrent of the D.C. transmission lines has the rated value (the A.C.voltages also have the rated values), the control voltage E_(c)corresponding to the advanced control angle β for attaining theprescribed extinction angle γ is obtained. When the current of the D.C.transmission lines changes, the advanced control angle β increases ordecreases in correspondence with the change, and the extinction angle γis maintained substantially constant.

There will now be explained the operation at the voltage change of theA.C. system to which this invention is primarily devoted. Let it besupposed that the current of the D.C. transmission lines is of the ratedvalue. Where the voltages of the A.C. system are of the rated values (p=1), the output of the operational amplifier A₁ is zero, and the controlvoltage E_(c) becomes the value corresponding to the advanced controlangle β for attaining the extinction angle γ as previously stated. When,for example, the phase-a one-line earthing arises as in FIG. 2 or FIG.3, the phase voltage V_(a) drops. In consequence, the positive voltageof the output of the amplifier AB becomes small in the absolute value.Accordingly, the positive output voltage of the amplifier AB becomessmaller in the absolute value than the negative bias voltage V_(BB), andthe voltage obtained by adding the voltage V_(BB) and the output voltageof the amplifier AB becomes a negative value. As the quantity p becomessmaller, the sum becomes greater. The output of the operationalamplifier A₁ is opposite in the polarity to the sum value. Since it issubjected to the addition by the operational amplifier A₂, the change ofthe advanced control angle β attendant upon the change of the quantity pbecomes as the straight line F shown in FIG. 7, and the purpose isachieved. The value F at p= 1.0 turns to a value determined by thecurrent I_(d) and the voltage V_(BB) ', and the positive voltage of theoutput of the amplifier A₁ increases with the decrease of the quantityp, so that the control voltage E_(c) becomes smaller. As the result, theretarded control angle α decreases, while the advanced control angle βincreases. Constants may be set so that the inclination of the variationmay become equal to the inclination of the straight line F in FIG. 7.

When the short-circuit between the phase-a and phase-b arisessubsequently, the line voltage V_(ab) drops more, and hence, the outputof the bridge B₄ is selected. As stated before, the advanced controlangle β corresponding to the drop width of the line voltage V_(ab) isobtained.

FIG. 13 is a block diagram which shows an example of the gate pulsephase shifter AP. In the figure, PT_(a) ; PT_(b) and PT_(c) designatethe potential transformers shown in FIG. 1, E_(c) designates a terminalfor introducing the output of the operational amplifier A₂ shown in FIG.11, and P₁ ; P₂ . . . and P₆ designate the gate pulses to be applied tothe respective arms constructed of the thyristor valves V₁ ; V₂ . . .and V₆.

In the example of FIG. 13, the synchronizing power sources (the linevoltages of the A.C. system in the illustrated example) are subjected tothe waveform conversion into square waves in a waveform shapingportion 1. The square waves are not directly impressed on a gate pulsephase portion 2. A synchronous oscillator which is synchronized with thesynchronizing power sources and which has a frequency being six timeshigher, is constructed. The output of the oscillator is put by a ringcounter into six parts, which are used as synchronous inputs of the gatepulse phase shifting portion 2. According to this example, the change ofthe output gate pulse phase responsive to the change of the controlvoltage is highly speedy as in the general gate pulse phase shiftercircuits. Moreover, the gate pulse interval is constant because it isdetermined by the single oscillator. The synchronization may be put intoa phasic relation fixed with the voltages of the A.C. system, andrequires only to follow a gentle fluctuation of the frequency of thevoltages of the A.C. system. Therefore, it is not feared that thesynchronization will pull out.

Outputs corresponding to the positive and negative half waves of therespective line voltages of the A.C. system are obtained by thepotential transformers PT₁ -PT₃ and waveform converter circuits F₁ -F₆.The outputs from the circuits F₁, F₂ . . . and F₆ are applied torespectively corresponding differentiation circuits D₁, D₂ . . . and D₆.Outputs from flip-flop circuits FO₁, FO₂ . . . and FO₆ are applied torespectively corresponding integration circuits I₁, I₂ . . . and I₆.From the differentiation circuits D₁, D₂ . . . and D₆, only positivepulses are derived. They are impressed on set terminals S of flip-flopcircuits FF₁, FF₂ . . . and FF₆ at the next stage, and set the flip-flopcircuits. These flip-flop circuits are reset in such way that outputsfrom flip-flop circuits RC₁, RC₂ . . . and RC₆ constituting the ringcounter RC are impressed on reset terminals R thereof. The width of theoutputs of the six flip-flop circuits FF₁ - FF₆ or the magnitude of avoltage corresponding thereto indicates the phase difference between thephase of the synchronizing power sources and that of the ring counteroutputs. An adder AD produces a voltage corresponding to a period duringwhich the outputs of the six flip-flop circuits FF₁ - FF₆ continue. Adifferential amplifier DF evaluates the voltage difference between theoutput of the adder AD and a phase setpoint given at a terminal PH. Theoutput of the differential amplifier DF is smoothed by a filter FL,amplified by a D.C. amplifier A', and applied to a voltage-controlledoscillator VCO. The oscillator VCO oscillates at a frequency which isproportional to the input voltage. The output of the oscillator VCO isapplied to the ring counter RC. The flip-flop circuits RC₁ - RC₆constituting the ring counter RC have the output of the oscillator VCOimpressed on reset terminals R thereof, and have output change signalsof the different ones of the flip-flop circuits RC₁ - RC₆ impressed onset terminals S thereof. Only one of the flip-flop circuits RC₁ - RC₆ isnormally set at "1." Each time the pulse is applied from the oscillatorVCO, the position of the state "1" shifts in the order of the suffixesof the flip-flop circuits RC₁ - RC₆. The flip-flop circuits FO₁ - FO₆have set terminals S and reset terminals R. The flip-flop circuit FO₁ isset by the output of the flip-flop circuit RC₁, while it is reset by theoutput of the flip-flop circuit RC₄. The flip-flop circuit FO₂ is set bythe output of the flip-flop circuit RC₂, while it is reset by the outputof the flip-flop circuit RC₅. The others are similarly operated.

As previously stated, the outputs of the flip-flop circuits FO₁ - FO₆are respectively applied to the integrators I₁ - I₆.

The operation of the circuit in FIG. 13 will now be explained.

The mean value of the output of the adder AD is proportional to thedifference in phase between the synchronizing power sources and theoutputs of the ring counter RC. The terminal PH is given the setpoint ofthe phase difference. When the ring counter outputs lag over thesynchronizing power sources to an amount exceeding the setpoint, theoutput of the adder AD becomes greater than the voltage of the setpointterminal PH. The output of the D.C. amplifier A' increases, thefrequency of the voltage-controlled oscillator VCO rises, and the phasedifference decreases. When the phase of the ring counter outputs leadsbeyond the setpoint, the frequency of the oscillator VCO lowersconversely, and the phase is retarded. Accordingly, the phase of theoutputs of the ring counter RC becomes a value equal to the setpointgiven to the set terminal PH and is settled. Where the frequency of thesynchronizing power sources varies, the ring counter outputs willgradually deviate with respect to the synchronizing power sources if thefrequency of the oscillator VCO is fixed. Consequently, the frequency ofthe oscillator VCO varies for the same reason as stated above, and thesame phasic relation as that before the frequency variation isestablished. Assuming now that the phases are set at 60 degrees theoutput of the flip-flop RC₂ is at a position of a lag of 60 degrees overthe output of the waveform converter circuit F₁ in FIG. 13. Accordingly,the output of the flip-flop RC₁ as leads by 60 degrees over that of theflip-flop RC₂ is inphase with the output of the waveform convertercircuit F₁. Since the flip-flop FO₁ is set by the flip-flop RC₁ and isreset by the flip-flop RC₄, it has an output width of 180 degrees as thewaveform converter circuit F₁ and is inphase with the circuit F₁.Likewise, where the synchronizing power sources are balanced, theoutputs of the flip-flops FO₂ - FO₆ have the same phases and waveformsas those of the waveform converter circuits F₂ - F₆. Where thesynchronizing power sources become unbalanced, the widths of the outputsof the flip-flops FF₁ - FF₆ become respectively different. However, theyare smoothed by the filter FL, and the oscillator VCO continues theconstant oscillation. Therefore, the outputs of the flip-flops RC₁ - RC₆and accordingly those of the flip-flops FO₁ - FO₆ are providedaccurately at the interval of 60 degrees and continue by 180 degrees.The characteristic as in FIG. 12 is therefore fulfilled by introducingthe outputs of the flip-flops FO₁ - FO₆ into the integration circuitsI₁ - I₆, comparing the outputs of the integration circuits I₁ - I₆ withthe control voltage E_(c) by respective comparators C₁ - C₆ andproducing the pulse outputs in places where they coincide.

When the control voltage E_(c) is corrected according to the least oneof the phase voltages and the line voltages as in FIG. 11, the gatepulse interval-fixing control is satisfied and besides the stablerunning of the inverter is possible.

FIG. 14 is a block diagram showing a further example of the gate pulsephase shifter which can be used for this invention. FIG. 15 is awaveform diagram for explaining the operation of the circuit in FIG. 14.The circuit has been published in `IEEE Summer Power Meeting Paper NO TO640-PWR,` and it is mentioned herein as the example of the gate pulsephase shifter which can be employed in case of performing thisinvention.

The operation of a pulse generator PG in FIG. 14 will be described. Inthe figure, VCC represents a voltage-controlled current source whichprovides a current of a magnitude proportional to an input voltageV_(c2). CON denotes a capacitor, and VCOM a comparator. The comparatoroperates and generates a pulse V_(p) when the terminal voltage V_(c) ofthe capacitor CON becomes larger by ΔV/2 than a phase control signalV_(c1). The pulse V_(p) drives a capacitor discharging circuit CD, tokeep the capacitor CON discharged until the terminal voltage V_(c)becomes smaller by ΔV/2 than the phase control signal V_(c1). Theappearance of this operation can be easily apprehended from the waveformdiagram in FIG. 15. The velocity Δ at which the terminal voltage V_(c)rises is proportional to the output current of the current source VCCand accordingly to the input voltage V_(c2). While the phase controlsignal V_(c1) is constant, the pulses V_(p) are generated at an intervalof 60 degrees. When the voltage V_(c1) increases as shown at ΔV_(c1),1in the figure, the phase of the pulse V_(p) changes by Δα₁ in thelagging direction. In contrast, when the voltage V_(c1) decreases asshown at ΔV.sub. c1,2, the phase of the pulse V_(p) instantly leads byΔα₂. The magnitudes of Δα₁ and Δα₂ are proportional to ΔV.sub. c1,1 andΔV.sub. c1,2, respectively. Shown at SR is a shift register. It is acircuit which distributes the pulses V_(p) as the gate pulses to therespective arms of the inverter as constructed of the thyristor valvesV₁ - V₆. The outputs P₁ - P₆ of the circuit SR are the gate pulses ofthe respective arms of the inverter. The other part of the circuitarrangement in FIG. 14 is a circuit for establishing the synchronizationwith the voltages of the A.C. system. AM indicates a circuit formeasuring the actual retarded control angle α of the inverter. FL₁ andFL₂ designates filters. As apparent from FIG. 15, the output α_(ref) ofthe filter FL₁ is equal to the phase control signal V_(c1). Accordingly,this value is made a reference value, and an α control circuit ACoperates to control the gradient Δ of the terminal voltage V_(c) inorder that the output α_(act) of the filter FL₂ may become equal to theoutput α_(ref) of the filter FL₁. Thus, the pulse generator PG operatesin synchronism with the A.C. system to which the inverter is connected.V_(c21) denotes a voltage proportional to the frequency of the A.C.system. It controls the gradient Δ of the voltage V_(c) through an adderADF according to a change of frequency, so as to always obtain theretarded control angle α equal to an electrical angle appointed by thephase control signal V_(c1). Since the time constant of the filter FL₂is set at a large value, the pulse phase shifter in FIG. 14 has the samefunction as the circuit in FIG. 13. Of course, the control voltage E_(c)in FIG. 11 is introduced as the control voltage indicated by V_(c1) inFIG. 14.

As described above, in accordance with this invention, the stablerunning can be ensured even when, in case of employing the pulse phaseshifter of the gate pulse interval-fixing control system, the voltage ofthe A.C. system drops due to any fault arising in the A.C. system.

While the connection of the transformer for the inverter has beenexplained above as being the star - star ( ) connection, this inventionis applicable without any substantial change to a case where thetransformer is of the star - delta ( Δ) connection. In this case, thereholds the relation that, at the earthing fault, the drop of the phasevoltage is larger than the drop of the commutation voltage and that, atthe short-circuit fault, the drop of the line voltage is the largest. Itis necessary in this case that the phases of the synchronizing powersources to be applied to the gate pulse phase shifter are made differentfrom those in the case of the star - star ( ) connection.

Where the connection of the transformer for the inverter is the star -star ( ) connection, the commutation voltage is equal to the linevoltage on the primary side of the transformer. As in FIG. 13,therefore, the voltage transformers PT_(a), PT_(b) and PT_(c) are of thestar - star ( ) connection and the voltage transformers PT₁, PT₂ and PT₃are of the delta - star (Δ ) connection, so that the line voltages ofthe A.C. system are applied to the waveform converter circuits F₁ - F₆.

Where the connection of the transformer for the inverter is the star -delta ( Δ) connection, the voltage transformers PT_(a), PT_(b) andPT_(c) in FIG. 13 may be brought to the star - delta ( Δ) connection, toform voltages corresponding to the commutation voltages, and the voltagetransformers PT₁, PT₂ and PT₃ may be brought to the delta - star (Δ )connection, to apply the commutation voltages to the waveform convertercircuits F₁ - F₆.

Since the voltage transformers PT_(a), PT_(b) and PT_(c) are not alwaysused exclusively for the gate pulse phase shifter, they cannot bebrought to the star - delta ( Δ) connection in some cases. In suchcases, a method to be stated below can be relied on. This inventionconsists in the system of intending to make the control in such way thatthe voltage phase of the A.C. system in the normalcy is referred to asthe phase of the synchronizing power sources. Therefore, it is notnecessarily required to employ the commutation voltages as thesynchronizing power sources of the gate pulse phase shifter. Where thetransformer connection is the star - delta ( Δ) connection, the phasevoltages V_(a), V_(b) and V_(c) on the A.C. side of the transformer forthe inverter as become inphase with the commutation voltages in thenormalcy of the A.C. system may be used as the synchronizing powersources without any change.

In this case, both the voltage transformers PT_(a), PT_(b) and PT_(c)and the voltage transformers PT₁, PT₂ and PT₃ in FIG. 13 may be made thestar - star ( ) connection.

While the curve E in FIG. 7 has been approximated by the straight line Fin the embodiment of FIG. 13, it is to be understood that a betterapproximation is achieved by a polygonal line which couples, forexample, the value of the curve E at p= 1.0, the intersection pointbetween the curves E and C, and the value of the curve E at p= 0. Sinceany well-known polygonal line circuit can be utilized to this end, aconcrete example is not specifically explained.

I claim:
 1. In a control system for an inverter connected to an A.C.system through a transformer for the inverter, an improved invertercontrol system comprising:first means for receiving a control voltageand for generating, at an advanced control angle, phase-shifted gatepulses in synchronism with voltages in-phase with commutation voltagesapplied to said inverter during the normal condition of said A.C.system, and for applying said gate pulses to respective arms of saidinverter at a fixed interval; and second means, responsive to a changein at least one of the phase voltages and line voltages of said A. C.system, for correcting said control voltage in accordance with saidchange.
 2. An improved inverter control system according to claim 1,wherein said first means comprises means for generating saidphase-shifted gate pulses in direct synchronism with said commutationvoltages.
 3. An improved inverter control system according to claim 1,wherein said first means comprises means for generating saidphase-shifted gate pulses in direct synchronism with the phase voltagesof said A.C. system.
 4. An improved inverter control system according toclaim 1, wherein said first means comprises means for generating saidphase-shifted gate pulses in direct synchronism with the line voltagesof said A.C. system.
 5. In a control system of an inverter connected toan A.C. system through a transformer for the inverter, an invertercontrol system comprising an oscillator which outputs an oscillationfrequency responsive to an input voltage, first means to divide theoutput frequency of said oscillator, second means to derive a phase ofvoltages inphase with commutation voltages being applied to saidinverter in the normalcy of said A.C. system, third means to derive adifference in phase between an output of said first means and an outputof said second means, fourth means to convert an outut of said thirdmeans into a voltage and to add thereto a signal for regulating into apredetermined relation the output phase of said oscillator and saidphase of said voltages inphase with said commutation voltages, thus tobring the sum voltage to said input voltage of said oscillator, and agate pulse phase shifter into which a control voltage for regulating aphase to output gate pulses thereat is introduced and which outputs saidgate pulses at an advanced control angle corresponding to said controlvoltage, said control voltage being corrected by the use of a least oneof phase voltages or line voltages of said A.C. system.
 6. The invertercontrol system according to claim 5, wherein said voltages inphase withsaid commutation voltages, said commutation voltages themselves areadopted.
 7. The inverter control system according to claim 5, wherein assaid voltages inphase with said commutation voltages, said phasevoltages or line voltages of said A.C. system are adopted.
 8. In acontrol system of an inverter connected to an A.C. system through atransformer for the inverter, an inverter control system comprising agate pulse phase shifter including a capacitor whose charging speed iscontrolled by a current dependent upon a voltage corresponding to afrequency of said A.C. system and a retarded control angle of saidinverter, and a circuit which, when a charging voltage of said capacitorand a control voltage are compared and are in a predetermined relation,outputs gate pulses and controls discharging of said capacitor, saidcontrol voltage being corrected by the use of a least one of phasevoltages or line voltages of said A.C. system.